As integrated circuit designs continue to increase in both complexity and density, design methodologies are challenged to create circuits that use Design-For-Test (DFT) techniques to improve the testability and the quality of the final product. Test methodologies are also challenged to create high-quality, low cost test solutions.
One conventional design methodology includes the process of initially designing an integrated circuit using a software design tool, simulating the overall functionality of the design or individual circuits within the design, and then generating test vectors for testing the overall function of the design. The test vectors are typically generated by an automated software tool (e.g., an Automatic Test Pattern Generator or “ATPG”) that provides a particular degree of fault coverage or fault simulation for the circuitry in the product. These test vectors are then typically provided in a computer readable file to Automatic Testing Equipment (ATE) or testers. The ATE is used in a manufacturing environment to test the die at wafer sort and in packaged tests. As integrated circuit designs become more complex and operate at higher speeds, they place more demands on the testing equipment. This tends to increase the cost of ATEs and, thus, tends to increase manufacturing costs. Additionally, as integrated circuit designs become more complex, the time required to test the circuits increases. This also tends to increase manufacturing costs.
During wafer-level testing of a die, test signals are provided through input or input/output (I/O) bond pads on the die, and the test results are monitored on output or I/O bond pads. The good die that pass the wafer-level test are singulated and typically packaged by electrically connecting the bond pads to the package by means of bond wires, solder balls, or other contact structures. To accommodate the bonding wires or solder balls, the bond pads are generally very large relative to the circuit elements of the integrated circuit. Typical bond pad sizes are on the order of 100 μm (microns)×100 μm (4 mils×4 mils). The bond pads are also typically aligned in regular patterns such as peripherally along the outside perimeter of the die, in a grid pattern, or in a column or row generally through the center of the die (lead-on-center).
To improve test coverage of individual circuits, DFT tools have been developed to embed test circuitry into the design itself. For example, Built-In Self-Test (BIST) circuitry can be inserted into the design to test individual circuit blocks. BIST is particularly useful for testing circuit blocks that are not readily accessible by bond pads of the device under test (DUT). Automated DFT tools (such as those provided by Mentor Graphics of Wilsonville, Oreg.) for generating BIST circuitry, such as memory BIST for testing memory blocks and logic BIST for testing logic blocks, are well known. The results of tests conducted by BIST circuitry are provided directly to external I/Os, or are indirectly provided to the external I/Os through boundary scan circuitry that may be included in the design. Additional internal embedded test circuitry such as SCAN chain circuitry may also be added to the design to increase the internal testability of internal sequential designs.
If a die already has all of its peripheral, grid, or lead-on-center bond pad locations dedicated to a device function, then adding additional bond pads in the predetermined bond pad alignment to support the on-chip testing circuitry can result in a substantial increase in the size of the die. This tends to have a corresponding increase in the cost of the die. Generally, larger die are more prone to defects and consequently more expensive to manufacture. Additionally, on-chip testing circuitry can result in a significant increase in test time as many clock cycles may be required to load test input data and subsequently output test results from a few available bond pads. On-chip testing circuitry also does not allow for direct external access to internal circuit nodes. Test input data and test results must pass through the SCAN circuitry or BIST circuitry before it can be monitored. This introduces additional circuits that can mask failures in the circuit intended to be tested, or can introduce new failures caused by SCAN or BIST circuitry.
Additionally, many designs are I/O limited since only a limited number of leads (e.g., bond wires) may be accommodated in a given packaging scheme. Moreover, to test I/O functionality of a die, these same lead locations must be used. It would be advantageous to access more points in a circuit, especially for testing. It would also be advantageous if the access points could be located with a high degree of positional freedom. Small size, large number, and arbitrary or selective positioning of the access points would also be advantageous.
With embedded test circuitry, the design methodology of an integrated circuit includes the process of: initially designing the integrated circuit using a software design tool; simulating the overall functionality of the integrated circuit or individual circuits within the design; generating embedded test circuitry to test individual circuits or circuit blocks in the design; and generating test vectors for functionally testing the device by an ATE.
The amount of embedded test circuitry to add to a particular design typically requires balancing the benefits of increased fault coverage and potentially decreased test time (e.g., as compared with an ATE) with the disadvantages of increasing both the die size and probability of fabrication defects which each result in increased manufacturing cost of the end product. At one extreme, designs could include elaborate embedded test circuits that test every circuit node of all internal circuits, however, these designs would be prohibitively expensive as the die size would primarily be a function of the size of the test circuitry. At another extreme, designs could include no embedded test circuitry and rely solely on test vectors supplied by an ATE to test the functionality of the design at the wafer level or in packaged form. This latter approach, however, tends to provide reduced fault coverage, a lower product quality, and increase manufacturing costs by using expensive ATEs and by increasing test times. One approach to minimize the cost of using expensive ATEs is disclosed in U.S. Pat. No. 5,497,079 (the '079 patent). The '079 patent condenses the general functions of the ATE into a general function test chip that, under the control of a host computer can test another semiconductor chip. The test chip can be disposed on a probe card or brought into electrical contact with the chip to be tested through a motherboard. Another approach is disclosed in U.S. application Ser. No. 08/784,862, filed Jan. 15, 1997, in which wafer level test of semiconductor chips is performed by test chips that have general purpose test circuitry.
In between the two extremes, typical integrated circuit designs strike a balance between the amount of embedded circuitry and tests that will be performed by an ATE. Typically, embedded circuitry is limited to approximately 5-15% of the total die area of the design, and test vectors are generated for an ATE to test the overall function of the design. This balance, however, results in less than optimal fault coverage while still requiring the use of expensive ATEs.
It is desirable to have design and test methodologies that break the direct correlation between fault coverage or testability and the cost of testing or manufacturing a design.